Monday, September 16
EDA Interactive Workshop TBA
EDA Interactive Workshop TBA
EDA Invited Talk TBA
EDA Invited Talk TBA
1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation
Yujie Zhou
Yujie Zhou received the B.S. degree in electrical engineering from University of Illinois Urbana-Champaign (UIUC), Urbana, IL,USA, in 2019. He is currently pursuing the Ph.D. degree in electrical engineering with UIUC. His research interests include ESD, device physics, compact modeling, and TCAD.
1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation
1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming
Kuo-Hsuan Meng
Kuo-Hsuan Meng received his B.S. degree from the Department of Electronics Engineering, and M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2007, respectively. He received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, in 2015. He worked at Freescale / NXP Semiconductors, Austin, TX, from 2015 to 2021. He joined Silicon Laboratories, Austin, TX, since 2021. His research interests include ESD protection network design, I/O library architecture, and CAD/EDA for SoC integration and ESD/latch-up design verification.
1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming
Author's Corner for 1A.1 and 1A.2
Kuo-Hsuan Meng
Kuo-Hsuan Meng received his B.S. degree from the Department of Electronics Engineering, and M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2007, respectively. He received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, in 2015. He worked at Freescale / NXP Semiconductors, Austin, TX, from 2015 to 2021. He joined Silicon Laboratories, Austin, TX, since 2021. His research interests include ESD protection network design, I/O library architecture, and CAD/EDA for SoC integration and ESD/latch-up design verification.
Yujie Zhou
Yujie Zhou received the B.S. degree in electrical engineering from University of Illinois Urbana-Champaign (UIUC), Urbana, IL,USA, in 2019. He is currently pursuing the Ph.D. degree in electrical engineering with UIUC. His research interests include ESD, device physics, compact modeling, and TCAD.
Author's Corner for 1A.1 and 1A.2
1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration
1A.4 Substrate NPN Extraction from Capacitance Field Solver
Chuan Xu
Dr. Chuan Xu received the B.S. and the M.S. from Peking University. He received the Ph.D. from University of California at Santa Barbara in 2012. During his Ph.D. program, he interned with IBM T. J. Watson Research Center and Mentor Graphics Corporation. In 2012, he joined the Device Modeling Team of Legacy Maxim Integrated (acquired by Analog Devices since 2021). His current research interests include modeling of active devices, parasitic devices, interconnects and packages in VLSI circuits. He has authored or co-authored over 40 journal and conference papers.
1A.4 Substrate NPN Extraction from Capacitance Field Solver
1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
Subhadeep Ghosh
Subhadeep Ghosh received his Bachelor's Degree in Electronics from Jadavpur University, Kolkata, India, and Masters Degree in Electronics from Indian Institute of Technology, Kharagpur, India. He joined Texas Instruments in Bangalore, India in 2005 and has since worked on Reliability EDA development for EMIR analysis, Transistor reliability and ESD. Currently he leads the EDA Development for Reliability, ESD and IR-drop analyses for all TI internal process nodes. He is a Member, Group Technical Staff (MGTS). His areas of expertise are design reliability, ESD EDA, digital design IR-drop, with methods enabling reliability as a specification through the design flow.
1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
Authors Corner for 1A.3, 1A.4, and 1A.5
Subhadeep Ghosh
Subhadeep Ghosh received his Bachelor's Degree in Electronics from Jadavpur University, Kolkata, India, and Masters Degree in Electronics from Indian Institute of Technology, Kharagpur, India. He joined Texas Instruments in Bangalore, India in 2005 and has since worked on Reliability EDA development for EMIR analysis, Transistor reliability and ESD. Currently he leads the EDA Development for Reliability, ESD and IR-drop analyses for all TI internal process nodes. He is a Member, Group Technical Staff (MGTS). His areas of expertise are design reliability, ESD EDA, digital design IR-drop, with methods enabling reliability as a specification through the design flow.
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
Chuan Xu
Dr. Chuan Xu received the B.S. and the M.S. from Peking University. He received the Ph.D. from University of California at Santa Barbara in 2012. During his Ph.D. program, he interned with IBM T. J. Watson Research Center and Mentor Graphics Corporation. In 2012, he joined the Device Modeling Team of Legacy Maxim Integrated (acquired by Analog Devices since 2021). His current research interests include modeling of active devices, parasitic devices, interconnects and packages in VLSI circuits. He has authored or co-authored over 40 journal and conference papers.